Vertically Stacked CVD-Grown 2D Heterostructure for Wafer-Scale Electronics

This paper demonstrates, for the first time, wafer-scale graphene/MoS₂ heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. A CVD-grown bulk MoS₂ layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable work-function electrode. The short vertical channel of the transistor is formed by sandwiching bulk MoS₂ between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene–MoS₂ junction and ITO–MoS₂ junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS₂/graphene heterostructure exhibits a current density exceeding 7 A/cm², a subthreshold swing of 410 mV/dec, and an on–off current ratio exceeding 10³. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS₂ and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR.