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Tunable Catalytic Alloying Eliminates Stacking Faults in Compound Semiconductor Nanowires

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journal contribution
posted on 08.02.2012, 00:00 by Hoseok Heo, Kibum Kang, Donghun Lee, Li-Hua Jin, Hyeon-Jun Back, Inchan Hwang, Miseong Kim, Hyun-Seung Lee, Byeong-Joo Lee, Gyu-Chul Yi, Yong-Hoon Cho, Moon-Ho Jo
Planar defects in compound (III–V and II–VI) semiconductor nanowires (NWs), such as twin and stacking faults, are universally formed during the catalytic NW growth, and they detrimentally act as static disorders against coherent electron transport and light emissions. Here we report a simple synthetic route for planar-defect free II–VI NWs by tunable alloying, i.e. Cd1–xZnxTe NWs (0 ≤ x ≤ 1). It is discovered that the eutectic alloying of Cd and Zn in Au catalysts immediately alleviates interfacial instability during the catalytic growth by the surface energy minimization and forms homogeneous zinc blende crystals as opposed to unwanted zinc blende/wurtzite mixtures. As a direct consequence of the tunable alloying, we demonstrated that intrinsic energy band gap modulation in Cd1–xZnxTe NWs can exploit the tunable spectral and temporal responses in light detection and emission in the full visible range.