Synergic Impacts of CF₄ Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO₂ Charge Trap and In–Ga–Zn–O Active Channel Layers

Charge-trap-assisted memory thin-film transistors (CTM-TFTs) using the engineered Al-doped HfO₂ (Al:HfO₂) CTL and In–Ga–Zn–O channel were fabricated and characterized to investigate the effects of CTL engineering processes including Al doping, CF₄ plasma treatment, and thermal annealing on nonvolatile memory performances. The CTM-TFTs using the Al:HfO₂ CTL treated with CF₄ plasma and postannealing (A4) exhibited a wider memory window of 13.0 V with a gate voltage sweep range of ±20 V and a higher program/erase (P/E) ratio of 8.0 × 10⁴ even with 1-μs-long P/E pulses. On the contrary, smaller memory windows were obtained to be 2.0, 3.5, and 4.5 V for the devices using the nontreated (A1), only CF₄ plasma-treated (A2), and only thermally annealed Al:HfO₂ CTLs (A3), respectively. Furthermore, for the A4 CTM-TFT device, the stable operational reliabilities including a long-term retention after a lapse of time for 10⁴ s and a robust data endurance after repeated P/E cycles of 10⁴ were obtained without any degradation of the P/E ratio. The improvement in memory device (A4) characteristics can be suggested to originate from the remarkable increase in the density of stable charge-trap sites located within the CTL and the effective suppression of undesirable trapping events in interfaces thanks to the optimum implementation of CTL engineering processes.