Sub-10 Nanometer Feature Size in Silicon Using Thermal Scanning Probe Lithography
journal contributionposted on 30.10.2017, 00:00 by Yu Kyoung Ryu Cho, Colin D. Rawlings, Heiko Wolf, Martin Spieser, Samuel Bisig, Steffen Reidt, Marilyne Sousa, Subarna R. Khanal, Tevis D. B. Jacobs, Armin W. Knoll
High-resolution lithography often involves thin resist layers which pose a challenge for pattern characterization. Direct evidence that the pattern was well-defined and can be used for device fabrication is provided if a successful pattern transfer is demonstrated. In the case of thermal scanning probe lithography (t-SPL), highest resolutions are achieved for shallow patterns. In this work, we study the transfer reliability and the achievable resolution as a function of applied temperature and force. Pattern transfer was reliable if a pattern depth of more than 3 nm was reached and the walls between the patterned lines were slightly elevated. Using this geometry as a benchmark, we studied the formation of 10–20 nm half-pitch dense lines as a function of the applied force and temperature. We found that the best pattern geometry is obtained at a heater temperature of ∼600 °C, which is below or close to the transition from mechanical indentation to thermal evaporation. At this temperature, there still is considerable plastic deformation of the resist, which leads to a reduction of the pattern depth at tight pitch and therefore limits the achievable resolution. By optimizing patterning conditions, we achieved 11 nm half-pitch dense lines in the HM8006 transfer layer and 14 nm half-pitch dense lines and L-lines in silicon. For the 14 nm half-pitch lines in silicon, we measured a line edge roughness of 2.6 nm (3σ) and a feature size of the patterned walls of 7 nm.