Vertically Stacked CVD-Grown 2D Heterostructure for Wafer-Scale Electronics
journal contributionposted on 13.09.2019 by Seongchan Kim, Young Chan Kim, Young Jin Choi, Hwi Je Woo, Young Jae Song, Moon Sung Kang, Changgu Lee, Jeong Ho Cho
Any type of content formally published in an academic journal, usually following a peer-review process.
This paper demonstrates, for the first time, wafer-scale graphene/MoS2 heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. A CVD-grown bulk MoS2 layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable work-function electrode. The short vertical channel of the transistor is formed by sandwiching bulk MoS2 between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene–MoS2 junction and ITO–MoS2 junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS2/graphene heterostructure exhibits a current density exceeding 7 A/cm2, a subthreshold swing of 410 mV/dec, and an on–off current ratio exceeding 103. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS2 and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR.