Low Operating Bias and Matched Input−Output Characteristics in Graphene Logic Inverters
journal contributionposted on 14.07.2010 by Song-Lin Li, Hisao Miyazaki, Akichika Kumatani, Akinobu Kanda, Kazuhito Tsukagoshi
Any type of content formally published in an academic journal, usually following a peer-review process.
We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene field-effect transistors (FETs). We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency. By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V. In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias. The inverters can be operated, with up to 4−7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs. For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications.