Assembly, Stability, and Electrical Properties of Sparse Crystalline Silicon Nanoparticle Networks Applied to Solution-Processed Field-Effect Transistors

Thin films of crystalline silicon nanoparticles (Si NPs) processed from liquid dispersions of NPs (NP inks) using printing-type deposition methods are currently being intensively investigated for the development of electronic and optoelectronic nanotechnologies. Various (opto)­electronic applications have already been demonstrated based on these materials, but so far, devices exhibit modest performance because of relatively low electrical conductivity and charge carrier mobility. In this work, we aim at unveiling the major factors affecting the long-range transport of charges in Si NP thin films. For this, we monitor the electrical properties of thin-film field effect transistors (FETs) as the active channel of the devices is gradually filled with Si NPs. To produce these FET devices featuring stable, sparse Si NP networks within the active channel, we developed a fabrication protocol based on NP deposition by device substrate immersion in a NP ink, made of Si NPs and chlorobenzene, followed by annealing and ultrasonication. We found that both the electrical conductivity and the charge carrier mobility of the FETs increase extremely rapidly as the device channel coverage with NPs increases. Thus, the NP network corresponds effectively to an inhomogeneous blend of conducting and insulating Si NPs, with the most efficient charge percolation paths involving only a fraction of the NPs. We discuss the factors that may lead to this behavior, in view of developing Si NP thin films with competitive charge transport characteristics.