Kim, Seongchan Kim, Young Chan Choi, Young Jin Woo, Hwi Je Song, Young Jae Kang, Moon Sung Lee, Changgu Cho, Jeong Ho Vertically Stacked CVD-Grown 2D Heterostructure for Wafer-Scale Electronics This paper demonstrates, for the first time, wafer-scale graphene/MoS<sub>2</sub> heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. A CVD-grown bulk MoS<sub>2</sub> layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable work-function electrode. The short vertical channel of the transistor is formed by sandwiching bulk MoS<sub>2</sub> between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene–MoS<sub>2</sub> junction and ITO–MoS<sub>2</sub> junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS<sub>2</sub>/graphene heterostructure exhibits a current density exceeding 7 A/cm<sup>2</sup>, a subthreshold swing of 410 mV/dec, and an on–off current ratio exceeding 10<sup>3</sup>. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS<sub>2</sub> and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR. Schottky barrier height;ITO;logic gates;bottom indium tin oxide;NOT;sandwiching bulk MoS 2;NOR;CVD-grown bulk MoS 2 layer;transistor;semiconducting MoS 2;electron injection barriers;tunable work-function electrode;CVD-Grown 2 D Heterostructure;NAND;chemical vapor deposition;CVD-grown monolayer graphene 2019-09-13
    https://acs.figshare.com/articles/journal_contribution/Vertically_Stacked_CVD-Grown_2D_Heterostructure_for_Wafer-Scale_Electronics/9822662
10.1021/acsami.9b11206.s001