Large-Area, Ultrathin Metal-Oxide Semiconductor Nanoribbon Arrays Fabricated by Chemical Lift-Off Lithography ZhaoChuanzhen XuXiaobin BaeSang-Hoon YangQing LiuWenfei BellingJason N. CheungKevin M. RimYou Seung YangYang AndrewsAnne M. WeissPaul S. 2018 Nanoribbon- and nanowire-based field-effect transistors (FETs) have attracted significant attention due to their high surface-to-volume ratios, which make them effective as chemical and biological sensors. However, the conventional nanofabrication of these devices is challenging and costly, posing a major barrier to widespread use. We report a high-throughput approach for producing arrays of ultrathin (∼3 nm) In<sub>2</sub>O<sub>3</sub> nanoribbon FETs at the wafer scale. Uniform films of semiconducting In<sub>2</sub>O<sub>3</sub> were prepared on Si/SiO<sub>2</sub> surfaces via a sol–gel process prior to depositing Au/Ti metal layers. Commercially available high-definition digital versatile discs were employed as low-cost, large-area templates to prepare polymeric stamps for chemical lift-off lithography, which selectively removed molecules from self-assembled monolayers functionalizing the outermost Au surfaces. Nanoscale chemical patterns, consisting of one-dimensional lines (200 nm wide and 400 nm pitch) extending over centimeter length scales, were etched into the metal layers using the remaining monolayer regions as resists. Subsequent etch processes transferred the patterns into the underlying In<sub>2</sub>O<sub>3</sub> films before the removal of the protective organic and metal coatings, revealing large-area nanoribbon arrays. We employed nanoribbons in semiconducting FET channels, achieving current on-to-off ratios over 10<sup>7</sup> and carrier mobilities up to 13.7 cm<sup>2</sup> V<sup>–1</sup> s<sup>–1</sup>. Nanofabricated structures, such as In<sub>2</sub>O<sub>3</sub> nanoribbons and others, will be useful in nanoelectronics and biosensors. The technique demonstrated here will enable these applications and expand low-cost, large-area patterning strategies to enable a variety of materials and design geometries in nanoelectronics.